Voltage, Throughput, Power, Reliability and Multicore Scaling
datasetposted on 01.01.2017, 00:00 by F Xia, A Rafiev, A Aalsaud, M Al-Hayanni, J Davis, J Levine, A Mokhov, A Romanovsky, R Shafik, A Yakovlev, S Yang
This repository contains original experimental data files that support the paper "Voltage, Throughput, Power, Reliability and Multicore Scaling" published in the August, 2017 issue of IEEE Computer Magazine. http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=7999145 on IEEE Xplore and http://eprint.ncl.ac.uk/file_store/production/231220/F208FCE7-A180-417A-A442-2D14D28A0D3B.pdf on open access. The two versions have different figure numbers and the following pertains to the figure numbers in the final version of IEEE Xplore. Any file with a name containing "FPGA" pertains to experiments on the FPGA part of a Xilinx Zynq ZC702 reported in Figures 2 and 4 of the paper. Files with A9 in the name contains results of experiments on the pair of ARM A9 processors on the same Xilinx Zynq ZC702 system as above. This data goes to Figure 4 of the paper. Files with names including "AnupsPC" include results from experiments on an Intel Core i7 processor. This data goes to Figure 4 of the paper. Files with names including "A7A15", "Odroid" and pure numbers such as 1000-2000 pertain to experiments on an Odroid Xu3 system with ARM big.LITTLE processors (ARM A7 and A15 cores). This data goes to Figure 4 of the paper. Files with "SRAM" in the names pertain to data from experiments on an asynchronous SRAM controller. This data goes to Figure 3 and Figure 4 of the paper. Files with "phi" in the names pertain to experimental data on an Intel Xeon Phi system. This data goes into Figure 4 of the paper. Other experimental results, pertaining to an asynchrounous 8051 microcontroller and a power-gated ARM M0 core support the findings in the paper, but because the publisher limits the total number of authors, did not make into the paper itself. This data is included in the directory with appropriately named files. The two Matlab (.mat) files in the directory are generated from the FPGA data and are used to generate Figure 2.