Network-on-Chip simulation results from ArchOn
datasetposted on 01.01.2018 by A Rafiev, F Xia, A Iliasov, A Romanovsky, A Yakovlev
Datasets usually provide raw data for analysis. This raw data often comes in spreadsheet form, but can be any collection of data, on which analysis can be performed.
The analysis for extra-functional properties like power and performance takes a critical role in the system design workflow. Hardware-software co-simulation is one of the commonly used ways to perform this type of analysis. However, with the modern development of many-core systems the problem of scalability is becoming a bottleneck for all analysis techniques including simulation, especially when a simple extrapolation from the single core results is unacceptable. In this work, we developed a framework aimed at the extra-functional analysis during the rapid prototyping stages of system design. The tool is based on stochastic modelling and simulation of cross-layer system representations. The concept of selective abstraction is applied to ensure a sufficient level of accuracy where it is needed, while reducing the complexity of the parts that are of less importance. A set of Networks-on-Chip topologies has been analysed and the data is presented here.